Easily Testable Array Multiplier Design Using VHDL

Abstract

Presents the design of variable array multipliers using VHDL. Multipliers of various operand sizes for different target processes can be implemented using the proposed VHDL based approach. The multipliers will be testable with a constant number of test vectors irrespective of the operand word lengths. A fast test pattern generator is also developed for simulation of the multiplier designs and subsequent testing of the fabricated chips.